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Switches-01a |
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In this section we are going to: - Examine Timers and Interrupts docs |
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TIMERS
Timers Preparatory Work: - Read Chapter 10 Timers of PS0294.pdf (Z8 Encore! XP F6482 Series Product Spec), starting on page 149 or read Using the eZ8 Timer application note AN029102.pdf - Keep handy the BSP API Reference manual RM0064.pdf to see how the API affects certain registers like CLKCTRLx
Timer Background Info: - The Timer Control Register TxCTL0 selects the timer operating mode (we'll use Continuous), prescale value, timer interrupt configuration, etc. - T0H & T0L (timer 0 high and low) contain the current 16-bit timer count value - Minimum time-out delay: set timer Reload High and Low Byte registers with 0x0001, and prescale value to 1 - Maximum time-out delay: set both registers with 0x0000, and prescale value to 128. If the Timer reaches 0xFFFF, the Timer rolls over to 0x0000 and continues counting
Initialize the Timer: - Disable interrupts before configuring the timers: DI() - Initialize the system clock: SYSCLOCK_Init() - Set timer to Continuous mode - Set the Prescaler value - Set the Timer 0 High and Low byte registers - Set the Reload Timer 0 High and Low byte registers - Set timer interrupt level - Enable timer output pin - Enable the timer Timer Registers:
T0H & T0L T0RH & T0RL TxCTL0 Control TxCTL1 Control TxCTL1 Control TxCTL2 TxSTAT Registers Registers Registers Parts 1&2 Registers Part 1 Registers Part 2 Registers Registers
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INTERRUPTS Interrupts Preparatory Work: Read Chapter 9 Interrupt Controller of PS0294.pdf (Z8 Encore! XP F6482 Series Product Spec). Read AN0141_(Nesting Interrupts with Z8 Encore! MCUs).pdf.
Interrupts Background Info: The Interrupt Control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 2 Register (IRQ2) to determine if any interrupt requests are pending. We'll be working with ports PA6 (SW2) and PA7 (SW7) of the IRQ2 Register.
Interrupt Registers:
IRQ0 IRQ1 IRQ2 IRQ3 IRQxENH & IRQxENL IRQES IRQSS0 IRQSS1 Register Register Register Register Registers Register Register Register
Note the IRQxEN High and IRQxEN Low Register bits map to each of the IRQx Registers but have been abbreviated to just IRQ0ENH & IRQ0ENL.
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